Analysis and Evaluation of Routing BIST Approaches for FPGAs
نویسندگان
چکیده
We present stuck-at and bridging fault simulation results for previously proposed Built-In Self-Test (BIST) approaches for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs). In addition, new BIST approaches are proposed and analyzed via fault simulation. The fault simulation results are used to compare and evaluate the fault detection capabilities and effectiveness of these BIST approaches for testing routing resources in FPGAs.
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